Clock frequency multiplier and method for multiplying a clock frequency

ABSTRACT

A clock frequency multiplier is provided. The clock frequency multiplier comprises a tracking circuit, a pulsing circuit, and a shaping circuit. The tracking circuit receives a clearing signal and a reference clock signal, outputs the quotient of the number of cycles of the reference clock signal in a cycle of the clearing signal divided by a first predetermined value. The pulsing circuit outputs a pulsing signal wherein the frequency of the pulsing signal is the frequency of the clearing signal multiplied by the first predetermined value. The shaping circuit divides the frequency of the pulsing signal by a second predetermined value and shapes the pulsing signal into a clock signal with a predetermined duty cycle, and outputs the divided and shaped pulsing signal as an output clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock frequency multiplier and amethod for multiplying a clock frequency. More particularly, the presentinvention relates to a clock frequency multiplier implemented with puredigital logic circuit, and a method thereof.

2. Description of the Related Art

Conventionally, a clock frequency multiplier is usually implemented witha phase lock loop (PLL) as the PLL has excellent output quality.However, the PLL includes some analogic components (such as operationalamplifier) and some passive components (such as resistor and capacitor).These components occupy a large area of an integrated circuit. Moreover,the components need separate simulation, or even require separate designand layout for different fabrication processes.

However, the superior output quality of the PLL may not be necessary forsome integrated circuits as the circuits only need stable frequencymultiplication. In such circumstances, it is desirable to have a clockfrequency multiplier offering stable frequency multiplication withoutincurring the problems as mentioned above.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a clock frequencymultiplier, which is implemented with pure digital logic circuit, offersstable frequency multiplication, and does not have the problems ofanalog components and passive components in fabrication processes. Andthe present invention is also directed to a method for multiplying aclock frequency.

According to an embodiment of the present invention, a clock frequencymultiplier is provided. The clock frequency multiplier comprises atracking circuit, a pulsing circuit, and a shaping circuit. The trackingcircuit receives a clearing signal and a reference clock signal, outputsthe quotient of the number of cycles of the reference clock signal in acycle of the clearing signal divided by a first predetermined value. Thepulsing circuit receives the clearing signal and the reference clocksignal, receives one of the quotient and a compensated quotient derivedfrom the quotient, and outputs a pulsing signal, wherein the frequencyof the pulsing signal is the frequency of the clearing signal multipliedby the first predetermined value. The shaping circuit receives theclearing signal, the reference clock signal and the pulsing signal. Theshaping circuit then divides the frequency of the pulsing signal by asecond predetermined value and shapes the pulsing signal into a clocksignal with a predetermined duty cycle, and outputs the divided andshaped pulsing signal as an output clock signal.

According to another embodiment of the present invention, a method formultiplying a clock frequency is provided. The method comprises acalculating step, a providing step, and a dividing and shaping step. Thecalculating step calculates a quotient of the number of cycles of areference clock signal in a cycle of a clearing signal divided by afirst predetermined value. The providing step provides a pulsing signalaccording to the clearing signal, the reference clock signal, and one ofthe quotient and a compensated quotient derived from the quotient,wherein the frequency of the pulsing signal is the frequency of theclearing signal multiplied by the first predetermined value. Thedividing and shaping step divides the frequency of the pulsing signal bya second predetermined value and shapes the pulsing signal into a clocksignal with a predetermined duty cycle according to the clearing signaland the reference clock signal. And then the dividing and shaping stepprovides the divided and shaped pulsing signal as an output clocksignal.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a block diagram showing a clock frequency multiplier accordingto an embodiment of the present invention.

FIG. 2 is a flow chart showing the flow of a method for multiplying aclock frequency according to an embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

Please refer to FIG. 1. FIG. 1 is a block diagram of the clock frequencymultiplier 100 according to an embodiment of the present invention. Theclock frequency multiplier 100 receives the input clock signal CLK andoutputs the output clock signal OUTPUT. The clock frequency multiplier100 comprises a ring oscillator 107, a frequency divider 101, a leadingedge detector 102, a tracking circuit 108, a compensation circuit 113, apulsing circuit 117, and a shaping circuit 122.

The ring oscillator 107 provides the high-frequency reference clocksignal REF. In this embodiment, the ring oscillator 107 comprises aninverter 106 connected as a delay loop.

The frequency divider 101 divides the frequency of the input clocksignal CLK by a predetermined value (denoted as N) and outputs a dividedinput clock signal 150. If we denote the frequency of the input clocksignal CLK as FCLK, then the frequency of the divided input clock signal150 is FCLK/N. The purpose of the frequency divider 101 is providingclock frequency division function in the clock frequency multiplier 100,in addition to the clock frequency multiplication, which will bedescribed below.

The leading edge detector 102 comprises D flip-flops 103 and 104, and anNAND gate 105. The D flip-flop 103 receives the divided input clocksignal 150 as its input D, and the reference clock signal REF as itsinput C. The D flip-flop 104 receives the output Q of the D flip-flop103 as its input D, and the reference clock signal REF as its input C.The NAND gate 105 receives the output Q of the D flip-flop 103 and theoutput Q of the D flip-flop 104, and outputs the clearing signal CLN. Asone skilled in the relevant art will easily understand, the clearingsignal CLN provides a low pulse at every rising edge of the dividedinput clock signal 150, and the frequency of the clearing signal CLN isthe same as that of the divided input clock signal 150, that is, FCLK/N.

The tracking circuit 108 provides a quotient 155 and a remainder 154,which are vital to the operation of the clock frequency multiplier 100.Their values are obtained from dividing the number of cycles of thereference clock signal REF in a cycle of the clearing signal CLN by apredetermined value (denoted as M). Actually, the tracking circuit 108provides the remainder 154 and the quotient 155 obtained in the lastcycle of the clearing signal CLN. Therefore, any frequency drift causedby factors such as temperature variation will be readily reflected inthe values of the remainder 154 and the quotient 155.

The tracking circuit 108 comprises a frequency divider 109, a counter110, a remainder latch 111, and a quotient latch 112.

The frequency divider 109 receives the clearing signal CLN and thereference clock signal REF, divides the frequency of the reference clocksignal REF by M and outputs a divided reference clock signal 151. Thefrequency divider 109 also provides the above remainder on its outputsignal 152, which the remainder latch 111 latches and outputs as theremainder 154 at the beginning of every cycle of the clearing signalCLN.

The counter 110 accumulates its output 153 at every rising edge of thedivided reference clock signal 151 and clears its output 153 at thebeginning of every cycle of the clearing signal CLN. As it can be seen,at the beginning of every cycle of the clearing signal CLN (or at theend of every cycle of the clearing signal CLN), the value of signal 153is equal to the quotient mentioned above. The quotient latch 112 latchesand outputs signal 153 as the quotient 155 at the beginning of everycycle of the clearing signal CLN.

A compensation circuit 113 outputs a compensated quotient 158 accordingto the quotient 155, the remainder 154, the clearing signal CLN, and thepulsing signal 159. In brief, the compensation circuit 113 serves toeven out intervals between consecutive pulses of the pulsing signal 159so that the output clock signal OUTPUT will have a more regularwaveform. The compensation circuit 113 has no substantial effect on thefrequencies of the pulsing signal 159 and the output clock signalOUTPUT, and is not included in some embodiments of the presentinvention. The compensation circuit 113 will be described in moredetails later. For now, let's assume the compensation circuit 113 doesnot exist and the compensated quotient 158 is the same as the quotient155.

A pulsing circuit 117 outputs a pulsing signal 159, whose frequency isthe frequency of the clearing signal CLN multiplied by M, i.e.,FCLK*M/N. The pulsing signal 159 serves as the base signal forgenerating the output clock signal OUTPUT. The pulsing circuit comprisesa comparator 118, a counting latch 119, a multiplexer 120, and an adder121.

Initially, the value of the pulsing signal 159 is zero. The multiplexerselects the output 161 of the adder 121 as its own output 162, which isprovided as the input of the counting latch 119. The counting latch 119latches and outputs signal 162 as its output 160 at every rising edge ofthe reference clock signal REF. The output 160 is in turn provided asthe input of the adder 121. In such a case, as depicted in FIG. 1, thevalue of signal 162 is the value of signal 160 plus one. Therefore, atevery rising edge of the reference clock signal REF, the output 160 ofthe counting latch 119 accumulates by one.

A comparator 118 compares the output 160 of the counting latch 119 andthe compensated quotient 158 (or the quotient 155 in embodiments withoutthe compensation circuit 113), and outputs the pulsing signal 159according to the comparison result. The comparator 118 outputs zero onthe pulsing signal 159 when its two inputs are unequal and outputs oneon the pulsing signal 159 when its two inputs are equal. When thepulsing signal 159 is equal to one, the multiplexer 120 will select zeroas its output 162 so that the counting of the output 160 of the countinglatch 119 will start over again. At the beginning of every cycle of theclearing signal CLN, the counting latch 119 clears its output 160 andthe counting of the output 160 will also start over again. According tothe above discussion, the pulsing signal 159 provides a high pulsewhenever the output 160 of the counting latch 119 is equal to thecompensated quotient 158 (or the quotient 155 in the embodiments withoutthe compensation circuit 113). Therefore, the frequency of the pulsingsignal 159 is FCLK*M/N.

A shaping circuit 122 receives the pulsing signal 159 and outputs theoutput clock signal OUTPUT. The shaping circuit 122 comprises the XOR(exclusive-or) gate 123 and the D flip-flop 124. The XOR gate 123receives the output clock signal OUTPUT and the pulsing signal 159. TheD flip-flop 124 receives the output of the XOR gate 123 as its input D,the reference clock signal REF as its input C, and the clearing signalCLN as its input CLR. The D flip-flop 124 provides its output Q as theoutput clock signal OUTPUT. As one skilled in the relevant art willeasily understand, the shaping circuit 122 divides the frequency of thepulsing signal 159 by a predetermined value (2 in this embodiment) andshapes the pulsing signal 159 into a clock signal with a 50% duty cycle.Here the “shaping” of the pulsing signal 159 means changing the dutycycle of the pulsing signal 159 to 50%. The output clock signal OUTPUTis simply the pulsing signal 159 put through the frequency division andthe shaping. The frequency of the output clock signal OUTPUT is(FCLK*M/N)/2.

Although the shaping circuit 122 of this embodiment changes the dutycycle of the pulsing signal 159 to 50%, please note that the presentinvention is not limited to a duty cycle of 50%. In other embodiments ofthe present invention, the shaping circuit can be implemented to shapethe pulsing signal into a predetermined duty cycle other than 50%.

Before we discuss the compensation circuit 113 in details, we have tounderstand the effect of compensation. Assuming, in this embodiment, thefrequency of the reference clock signal REF is 41 times that of theclearing signal CLN and the predetermined value M is equal to 6. Sincethere are 41 cycles of the reference clock signal REF in a cycle of theclearing signal CLN, let's denote the position of the first cycle of thereference clock signal REF as 1 and the position of the last cycle ofthe reference clock signal REF as 41. Table 1 below shows the effect ofcompensation on the pulsing signal 159. As it can be seen, withoutcompensation, the difference between the maximum pulse interval and theminimum pulse interval of the pulsing signal 159 is five. In otherwords, the maximum pulse interval is two times the minimum pulseinterval. This is caused by the remainder (5) of dividing 41 by thepredetermined value M (6). Such irregularity will also appear in theoutput clock signal OUTPUT. This is obviously undesirable.

On the other hand, if we distribute the remainder into the pulseintervals, i.e., “compensate” the pulse intervals, as evenly aspossible, we will get a much better result. As shown in the bottom rowof table 1, with compensation, the difference between the maximum pulseinterval and the minimum pulse interval of the pulsing signal 159 isonly one. Therefore, the output clock signal OUTPUT will be much moreregular. The compensation is achieved by simply postponing some pulsesof the pulsing signal 159. TABLE 1 the effect of compensation on thepulsing signal 159. Positions of Intervals between high pulsesconsecutive high pulses of the pulsing signal of the pulsing signal 159159 Without compensation 6, 12, 18, 24, 30, 36 5, 5, 5, 5, 5, 10 Withcompensation 6, 13, 20, 27, 34, 41 6, 6, 6, 6, 6, 5

In detail, the compensation circuit 113 comprises the counter 116, thecompensation calculator 114, and the adder 115. The counter 116accumulates its output 157 at every pulse of the pulsing signal 159 andclears its output 157 at the beginning of every cycle of the clearingsignal CLN. The purpose of counter 116 is keeping track of the number ofpulses of the pulsing signal 159 in a cycle of the clearing signal CLN.The compensation calculator 114 outputs the compensation signal 156 topostpone some pulses of the pulsing signal 159 according to theremainder 154, the output 157 of the counter 116, and the predeterminedvalue M. The value of the compensation signal 156 is the number ofcycles of the reference clock signal REF for which the next pulse of thepulsing signal 159 will be postponed. The compensation calculator 114has built-in tables for various combinations of the remainder 154, theoutput 157 of the counter 116, and the predetermined value M. Finally,the adder 115 outputs the sum of the quotient 155 and the compensationsignal 156 as the compensated quotient 158.

According to the above discussion, the clock frequency multiplier 100 inthis embodiment multiplies the frequency of the input clock signal CLKby a factor of (M/N)/2. The clock frequency multiplier 100 isimplemented with pure digital logic circuit, offers stable frequencymultiplication, and does not have the problems of analog components andpassive components in fabrication processes.

Now please refer to FIG. 2. FIG. 2 is a flow chart of a method formultiplying a clock frequency according to an embodiment of the presentinvention. The flow of the method is similar to the operation of theclock frequency multiplier 100 in the previous embodiment. The flowbegins at step 202.

In step 202, divide the frequency of the input clock signal by thepredetermined value N and provide the divided input clock signal. Thenin step 204, provide the clearing signal according to the divided inputclock signal and the reference clock signal such that the clearingsignal provides a low pulse at every rising edge of the divided inputclock signal and the frequency of the clearing signal is the same asthat of the divided input clock signal.

Steps 206 to 212 are for generating the quotient and the remainder inthe previous embodiment. In step 206, divide the frequency of thereference clock signal by the predetermined value M and output thedivided reference clock signal. And then in step 208, accumulate a firstcounting value in response to the divided reference clock signal, andclear the first counting value in response to the clearing signal. Instep 210, provide the first counting value as the quotient in responseto the clearing signal. Finally, in step 212, provide, in response tothe clearing signal, the remainder of the number of cycles of thereference clock signal in a cycle of the clearing signal divided by thepredetermined value M.

Steps 214 to 218 are for generating the compensated quotient in theprevious embodiment. In step 214, accumulate a second counting value inresponse to the pulsing signal and clear the second counting value inresponse to the clearing signal. Then in step 216, provide thecompensation signal according to the remainder, the second countingvalue, and the predetermined value M, to postpone some pulses of thepulsing signal. And then in step 218, add the quotient and thecompensation signal, and provide the sum as the compensated quotient.

Steps 220 and 222 are for generating the pulsing signal in the previousembodiment. In step 220, accumulate a third counting value in responseto the reference clock signal and clear the third counting value inresponse to the clearing signal and the pulsing signal. And then in step222, provide the pulsing signal according to the comparison of the thirdcounting value and the compensated quotient.

Finally, in step 224, divide the frequency of the pulsing signal by apredetermined value (2 in this embodiment). In the same time, shape thepulsing signal into a clock signal with a predetermined duty cycle (50%in this embodiment) according to the clearing signal and the referenceclock signal. And provide the divided and shaped pulsing signal as theoutput clock signal.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A clock frequency multiplier, comprising: a tracking circuit,receiving a clearing signal and a reference clock signal, outputting aquotient of the number of cycles of the reference clock signal in acycle of the clearing signal divided by a first predetermined value; apulsing circuit, receiving the clearing signal and the reference clocksignal, receiving one of the quotient and a compensated quotient derivedfrom the quotient, and outputting a pulsing signal, wherein thefrequency of the pulsing signal is the frequency of the clearing signalmultiplied by the first predetermined value; and a shaping circuit,receiving the clearing signal, the reference clock signal and thepulsing signal, dividing the frequency of the pulsing signal by a secondpredetermined value and shaping the pulsing signal into a clock signalwith a predetermined duty cycle, and outputting the divided and shapedpulsing signal as an output clock signal.
 2. The clock frequencymultiplier according to claim 1, wherein the tracking circuit comprises:a first frequency divider, receiving the clearing signal and thereference clock signal, dividing the frequency of the reference clocksignal by the first predetermined value and outputting the dividedreference clock signal; a first counter, incrementing an output of thefirst counter in response to the divided reference clock signal, andclearing the output of the first counter in response to the clearingsignal; and a quotient latch, latching and outputting the output of thefirst counter as the quotient in response to the clearing signal.
 3. Theclock frequency multiplier according to claim 2, wherein the trackingcircuit further comprises: a remainder latch, latching and outputting,in response to the clearing signal, a remainder of the number of cyclesof the reference clock signal in a cycle of the clearing signal dividedby the first predetermined value, wherein the remainder is provided bythe first frequency divider.
 4. The clock frequency multiplier accordingto claim 3, further comprising: a compensation circuit, outputting thecompensated quotient according to the quotient, the remainder, theclearing signal, and the pulsing signal, to even out intervals betweenconsecutive pulses of the pulsing signal.
 5. The clock frequencymultiplier according to claim 4, wherein the compensation circuitfurther comprises: a second counter, incrementing an output of thesecond counter in response to the pulsing signal and clearing the outputof the second counter in response to the clearing signal; a compensationcalculator, outputting a compensation signal according to the remainder,the output of the second counter, and the first predetermined value, topostpone some pulses of the pulsing signal; and a first adder,outputting a sum of the quotient and the compensation signal as thecompensated quotient.
 6. The clock frequency multiplier according toclaim 1, wherein the pulsing circuit further comprises: a countinglatch, latching an input of the counting latch as an output of thecounting latch in response to the reference clock signal and clearingthe output of the counting latch in response to the clearing signal; asecond adder, providing the output of the counting latch plus one as anoutput of the second adder; a multiplexer, selecting and outputting oneof the number zero and the output of the second adder according to thepulsing signal as the input of the counting latch; and a comparator,outputting the pulsing signal according to a comparison of the output ofthe counting latch and one of the quotient and the compensated quotient.7. The clock frequency multiplier according to claim 1, wherein thesecond predetermined value is two.
 8. The clock frequency multiplieraccording to claim 7, wherein the shaping circuit further comprises: anXOR gate, receiving the output clock signal and the pulsing signal; anda first D flip-flop, receiving the output of the XOR gate as the input Dof the first D flip-flop, the reference clock signal as the input C ofthe first D flip-flop, and the clearing signal as the input CLR of thefirst D flip-flop, providing the output Q of the first D flip-flop asthe output clock signal.
 9. The clock frequency multiplier according toclaim 1, further comprising: a second frequency divider, receiving aninput clock signal, dividing the frequency of the input clock signal bya third predetermined value and outputting the divided input clocksignal; and a leading edge detector, outputting the clearing signalaccording to the divided input clock signal and the reference clocksignal.
 10. The clock frequency multiplier according to claim 9, whereinthe leading edge detector further comprises: a second D flip-flop,receiving the divided input clock signal as the input D of the second Dflip-flop and the reference clock signal as the input C of the second Dflip-flop; a third D flip-flop, receiving the output Q of the second Dflip-flop as the input D of the third D flip-flop and the referenceclock signal as the input C of the third D flip-flop; and an NAND gate,receiving the output Q of the second D flip-flop and the output Q of thethird D flip-flop, providing an output of the NAND gate as the clearingsignal.
 11. The clock frequency multiplier according to claim 1, whereinthe reference clock signal is provided by an inverter connected as adelay loop.
 12. The clock frequency multiplier according to claim 1,wherein the predetermined duty cycle is 50%.
 13. A method formultiplying a clock frequency, comprising: calculating a quotient of thenumber of cycles of a reference clock signal in a cycle of a clearingsignal divided by a first predetermined value; providing a pulsingsignal according to the clearing signal, the reference clock signal, andone of the quotient and a compensated quotient derived from thequotient, wherein the frequency of the pulsing signal is the frequencyof the clearing signal multiplied by the first predetermined value; anddividing the frequency of the pulsing signal by a second predeterminedvalue and shaping the pulsing signal into a clock signal with apredetermined duty cycle according to the clearing signal and thereference clock signal, and providing the divided and shaped pulsingsignal as an output clock signal.
 14. The method according to claim 13,wherein the step of calculating the quotient further comprises: dividingthe frequency of the reference clock signal by the first predeterminedvalue and outputting the divided reference clock signal; accumulating afirst counting value in response to the divided reference clock signal,and clearing the first counting value in response to the clearingsignal; and providing the first counting value as the quotient inresponse to the clearing signal.
 15. The method according to claim 14,wherein the step of calculating the quotient further comprises:providing, in response to the clearing signal, a remainder of the numberof cycles of the reference clock signal in a cycle of the clearingsignal divided by the first predetermined value.
 16. The methodaccording to claim 15, further comprising: providing the compensatedquotient according to the quotient, the remainder, the clearing signal,and the pulsing signal, to even out intervals between consecutive pulsesof the pulsing signal.
 17. The method according to claim 16, wherein thestep of providing the compensated quotient further comprises:accumulating a second counting value in response to the pulsing signaland clearing the second counting value in response to the clearingsignal; providing a compensation signal according to the remainder, thesecond counting value, and the first predetermined value, to postponesome pulses of the pulsing signal; and adding the quotient and thecompensation signal and providing the sum as the compensated quotient.18. The method according to claim 13, wherein the step of providing thepulsing signal further comprises: accumulating a third counting value inresponse to the reference clock signal and clearing the third countingvalue in response to the clearing signal and the pulsing signal; andproviding the pulsing signal according to a comparison of the thirdcounting value and one of the quotient and the compensated quotient. 19.The method according to claim 13, wherein the second predetermined valueis two.
 20. The method according to claim 13, further comprising:dividing the frequency of an input clock signal by a third predeterminedvalue and providing the divided input clock signal; and providing theclearing signal according to the divided input clock signal and thereference clock signal such that the clearing signal provides a lowpulse at every rising edge of the divided input clock signal and thefrequency of the clearing signal is the same as that of the dividedinput clock signal.
 21. The method according to claim 13, wherein thepredetermined duty cycle is 50%.